Method and apparatus for electrical test of wiring patterns formed on a printed circuit board
US5744964A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 25, 1996 |
| Grant date | Apr 28, 1998 |
| Priority date | — |
| Expiry date | Jul 25, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/312
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
For a print-circuit board 10 of a good product, probes 31 and 32 are made to be electrically continuous with a ground plate 13 and a wiring pattern i respectively to measure a capacitance Cgi, which is then stored in a storage device 44. A capacitance Ci of a print-circuit board 10, the object of testing, is measured in a similar manner and a ratio .mu.=(average value Ca of a several measured capacitance value of the object of testing/(average value Cga of the corresponding measured capacitance values of the good product) is calculated. If Ci<Cgj(1-.DELTA.e0) or Ci>Cgj(1+.DELTA.e0), the measured capacitance values Ci and Cgjare excluded from the objects of calculation of the average values. If Cj<.mu..Cgj(1-.DELTA.e) or Cj>.mu..Cgj(1+.DELTA.e), a wiring j is judged to be defective and the resistance measuring method is employed to judge the details of the defect. The tolerance rate .DELTA.e0 and .DELTA.e are 0.15 and 0.02 respectively.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.