CMOS integrated semiconductor circuit

US5744996A · kind A · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Gunther Kotzle · Nagold, DE
• Volker Kreuter · Korschenbroich, DE
• Thomas Ludwig · Sindelfingen, DE
• Helmut Schettler · Waldenbuch, DE

Key dates

• Filing date: Jul 17, 1995
• Grant date: Apr 28, 1998
• Expiry date: Jul 17, 2015

Classification

• Technology area (CPC G): Physics
• CPC primary: G05F3/205
• WIPO field: Control
• WIPO sector: Instruments

Abstract

An integrated semiconductor circuit for reducing power consumption, employing CMOS technology in which a transistor pair can be operated stably at different supply voltages. At each supply voltage the transistors have an associated threshold voltage which can be set via the well and substrate bias voltages. The substrate of the transistor pair is connected to a substrate bias voltage generator circuit and the well is connected to a well bias voltage generator circuit. An input signal representing the level of the supply voltage sets the respective bias voltages corresponding to the level of the supply voltage. Thus, the threshold voltage of each transistor is adapted to the existing supply voltage, thereby ensuring stable operation of the transistor pair. A battery driven data processing system with the integrated semiconductor circuit can attain an approximate 100 fold extension of the operating time of the battery.