Timing diagram method for inputting logic design parameters to build a testcase for the logic diagram
US5745386A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 25, 1995 |
| Grant date | Apr 28, 1998 |
| Priority date | — |
| Expiry date | Sep 25, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/261
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A. system (i.e. a tool set) provides logic verification at the logic design level in which an external stimulus to the design is derived from a series of generalized timing diagrams that obey the interface protocols of the logic design under test. A timing diagram editor provides a graphical user interface that allows the logic designer to describe his or her logic in a general timing diagram format incorporating permutations of the interface specification. The output of the timing diagram editor is a file that describes the interfaces of the logic; this file can contain multiple timing diagrams that describe different interface interactions. A suitable simulation driver reads the file created by the timing diagram editor, learns the interfaces described therein, and uses simulation randomization algorithms to drive the interfaces with legal scenarios for the interfaces described in the timing diagram.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.