Edward J. Kaminski, Jr.
15Patents
3h-index
16Co-inventors
57Inventor score
Filing activity: Sep 25, 1995 → Jul 26, 2018
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US7089518B2 | Method and program product for modelling behavior of asynchronous clocks in a system having multiple clocks | Physics | 32 | Expired |
| US5745386A | Timing diagram method for inputting logic design parameters to build a testcase for the logic diagram | Physics | 18 | Expired |
| US7483825B2 | Method for the creation of a hybrid cycle simulation model | Physics | 14 | Active |
| US8364904B2 | Horizontal cache persistence in a multi-compute node, symmetric multiprocessing computer | Physics | 3 | Active |
| US10055327B2 | Evaluating fairness in devices under test | Physics | 2 | Active |
| US10061679B2 | Evaluating fairness in devices under test | Physics | 2 | Active |
| US9619312B2 | Persistent command parameter table for pre-silicon device testing | Physics | 1 | Active |
| US9892010B2 | Persistent command parameter table for pre-silicon device testing | Physics | 1 | Active |
| US10289512B2 | Persistent command parameter table for pre-silicon device testing | Physics | 1 | Active |
| US9524801B2 | Persistent command parameter table for pre-silicon device testing | Physics | 1 | Active |
| US10678670B2 | Evaluating fairness in devices under test | Physics | 0 | Active |
| US9378023B2 | Cross-pipe serialization for multi-pipeline processor | Physics | 0 | Active |
| US10671506B2 | Evaluating fairness in devices under test | Physics | 0 | Active |
| US7213122B2 | Controlling the generation and selection of addresses to be used in a verification environment | Physics | 0 | Expired |
| US9501283B2 | Cross-pipe serialization for multi-pipeline processor | Physics | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.