Circuit and method to externally adjust internal circuit timing
US5745430A · kind A · utility
7Cited by
3References
30Claims
0Family size
Assignees
Inventors
Key dates
| Filing date | Dec 30, 1996 |
| Grant date | Apr 28, 1998 |
| Priority date | — |
| Expiry date | Dec 30, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/3016
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A circuit and method of using a test mode to control the timing of an internal signal using an external control in an integrated circuit. The test mode is designed such that the timing of the internal signal is derived from the external control which can be arbitrarily controlled by a tester. The external signal can be applied to an existing pin for chip control, provided that there is no conflict between the test mode and the operation of the integrated circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.