Built-in self testing for the identification of faulty integrated circuit chips in a multichip module

US5745500A · kind A · utility

Assignee

• The United States of America as represented by the Secretary of the Army · US

Inventors

• Thyagaraju Damarla · Laurel, US
• Moon Jae CHUNG · Okemos, US
• Wei Su · Bel Air, US
• Gerald T. Michael · Waretown, US

Key dates

• Filing date: Oct 22, 1996
• Grant date: Apr 28, 1998
• Expiry date: Oct 22, 2016

Classification

• Technology area (CPC G): Physics
• CPC primary: G01R31/2884
• WIPO field: Measurement
• WIPO sector: Instruments

Abstract

A built-in self test method and circuit identifies a faulty integrated ciit chip in a multichip module. The built-in self test method first applies a test pattern to a multichip module having a plurality of integrated circuit chips and to a reference signal generator, generates a first and second reference signal representing test responses for a fault free multichip module, compresses the outputs from the multichip module into a first and second bit using a first and second linear space compressor, uses exclusive OR logic to combine the first bit with the first reference signal to produce a first fault detection output and to combine the second bit with the second reference signal to produce a second fault detection output, stores the first and second fault detection outputs in a pair of N-bit shift registers; compares the stored outputs to detect a fault condition, and applies a series of recursive logic operations to identify the faulty integrated circuit chip in the multichip module. The built-in self test circuit includes a test pattern generator, a reference signal generator, at least two linear space compressors, at least two N-bit shift registers, and a plurality of logic g…