Method and system for programming a gate array using a compressed configuration bit stream
US5745734A · kind A · utility
233Cited by
13References
39Claims
0Family size
Assignee
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Key dates
| Filing date | Sep 29, 1995 |
| Grant date | Apr 28, 1998 |
| Priority date | — |
| Expiry date | Sep 29, 2015 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M7/3084
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A generalized data decompression engine is incorporated within a field programmable gate array ("FPGA"). The generalized data decompression engine uses a general purpose data decompression technique such as, for example, a Lempel-Ziv type technique. During operation, a compressed configuration bit stream is received by the generalized data decompression engine in the FPGA and is decompressed thereby. A resultant decompressed configuration bit stream is then used to program logic cells within the FPGA.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.