Interconnect structure with an integrated low density dielectric
US5747880A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 18, 1996 |
| Grant date | May 5, 1998 |
| Priority date | — |
| Expiry date | Nov 18, 2016 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S148/118
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
This invention provides a semiconductor device and process for making the same with dramatically reduced capacitance between adjacent conductors and an interlayer dielectric construction which emphasizes mechanical strength, etch compatibility, and good heat transfer. This process can include applying a solution between conductors 24, and then gelling, surface modifying, and drying the solution to form an extremely porous dielectric layer 28. A non-porous dielectric layer 30 may be formed over porous layer 28, which may complete an interlayer dielectric and provide mechanical strength, heat transfer, and a solid layer for via etch. A novel process for creating the porous dielectric layer is disclosed, which can be completed at vacuum or ambient pressures, yet results in porosity, pore size, and shrinkage of the dielectric during drying comparable to that previously attainable only by drying gels at supercritical pressure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.