OR-plane memory cell array for flash memory with bit-based write capability, and methods for programming and erasing the memory cell array
US5748538A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 14, 1996 |
| Grant date | May 5, 1998 |
| Priority date | — |
| Expiry date | Nov 14, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2211/5644
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory cell array of a flash electrically erasable programmable read only memory (EEPROM) includes a plurality of transistor cells arranged in rows and columns. The sources of transistor cells in the same memory block are connected to a main source line through a control gate, as are the drains. The separate source and drains in the column direction are designed for a bit-based write capability. Writing, such as erasing or programming, of a selected transistor cell uses the Fowler-Nordheim tunneling method and can be accomplished due to the programming or erase inhibit voltage that is applied to non-selected transistor cells. The associated circuitry for bit-based writing, as well as methods of programming and erasing the memory cell array, with over-program and over-erase repair capability, are also disclosed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.