Memory device with on-chip manufacturing and memory cell defect detection capability
US5748545A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 3, 1997 |
| Grant date | May 5, 1998 |
| Priority date | — |
| Expiry date | Apr 3, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2201/81
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device with an on-chip manufacturing and memory cell defect detection capability includes a memory array with a plurality of memory cells that are organized in rows and columns, a plurality of word lines that interconnect respectively the rows of memory cells, and a plurality of bit lines that interconnect respectively the columns of memory cells. Global word line short and global word line open testing circuits are provided to detect the presence of a word line short or word line open condition. Local word line short and local word line open testing circuits are provided to identify the defective word line. Global bit line short and global bit line open testing circuits are provided to detect the presence of a bit line short or bit line open condition. A local bit line short/open testing circuit is used to identify the defective bit line. Short circuiting between word lines and bit lines, and the maximum and minimum threshold voltages of the memory cells can also be detected in the disclosed memory device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.