Sensing scheme for flash memory with multilevel cells
US5748546A · kind A · utility
42Cited by
54References
3Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 10, 1997 |
| Grant date | May 5, 1998 |
| Priority date | — |
| Expiry date | Apr 10, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2211/5632
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods and apparatus for determining the state of a memory cell having more than two possible states are disclosed. For a first embodiment, the state of a flash cell having n states, where n is a power of 2, is determined by selectively comparing the threshold voltage V.sub.t of a selected memory cell to (n-1) reference voltages. For every two states, a single comparator is provided such that the total number of comparators is equal to the number of bits stored in the memory cell.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.