Multi-bit test circuits for integrated circuit memory devices and related methods
US5748639A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 24, 1996 |
| Grant date | May 5, 1998 |
| Priority date | — |
| Expiry date | Apr 24, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/38
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for testing a plurality of data bits includes the steps of accepting the plurality of data bits at the test circuit, and comparing first and second data bits from the plurality of data bits to determine if the first and second data bits have a common data value. A first comparison signal is generated responsive to the comparison of the first and second data bits. The first comparison signal has a first logic state when the first and second data bits have a common data value and a second logic state when the first and second data bits have different data values. Third and fourth data bits from the plurality of data bits are compared to determine if the third and fourth data bits have a common data value. A second comparison signal is generated responsive to the comparison of the third and fourth data bits wherein the second comparison signal has the first logic state when the third and fourth data bits have a common data value and the second logic state when the third and fourth data bits have different data values.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.