Efficient three-dimensional layout method for logic cell arrays
US5748942A · kind A · utility
5Cited by
10References
3Claims
0Family size
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Key dates
| Filing date | Jun 7, 1995 |
| Grant date | May 5, 1998 |
| Priority date | — |
| Expiry date | Jun 7, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/39
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method by which a two-dimensional array of logic elements may be interconnected such that they may be modeled as a three-dimensional array, while minimizing routing crossings. The result is an arrangement that is highly efficient for implementation in a silicon die. The preferred model may be extended to a three-dimensional torus where opposing faces of the array are considered to be adjacent. Routing flexibility is increased by increasing local interconnect while minimizing interconnect crossover.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.