Semiconductor chip bonding method
US5749510A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Apr 12, 1996 |
| Grant date | May 12, 1998 |
| Priority date | — |
| Expiry date | Apr 12, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/07802
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A chip mounting section "H", defined on a flush surface of a substrate 1, is dissected into a plurality of subsections "E"--"E". Bond 2 is applied within the chip mounting section "H" on the flush surface of substrate 1 in a discrete manner so that a plurality of bonding bumps 2 are arranged within each region of subsection "E". A minimum clearance "L" between two bonding bumps 2, 2 in the same subsection "E" is smaller than a minimum clearance "D" between two bonding bumps 2, 2 belonging to adjacent to subsections "E" and "E". A chip 3 is mounted on plural bonding bumps 2 by applying a force thereon, thereby mashing plural bonding bumps 2 by a bottom surface of chip 3 without causing any void therein.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.