Method and structure for reducing short circuits between overlapping conductors
US5751019A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Dec 6, 1994 |
| Grant date | May 12, 1998 |
| Priority date | — |
| Expiry date | Dec 6, 2014 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D1/68
Abstract
Method and apparatus for reducing current leakage between overlapping conductive structures in a multi-layered integrated circuit device such as a thin film capacitor is described. A conductive structure operating as a raised lower electrode is preferably fashioned by step-like erosion using a photolithographic techniques atop a dielectric substrate. In accordance with this invention, the dielectric substrate itself is allowed to erode as well to space the conductive structure away from the problemmatic inner corners of the step. By so distancing such conductive structures, like electrodes, from these inside corners, even conventional deposition techniques can be used to fabricate a capacitive device of operational tolerance suitable for DRAM application without risk of unwanted electrode current leakage and possible shorting. By so separating, the capacitance of the device can be reliably increased by increasing the available three dimensional capacitor area and decreasing the film thickness rather than relying primarily on high permittivity dielectrics.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.