I.sub.DDQ -testing of bias generator circuit
US5751141A · kind A · utility
3Cited by
6References
6Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 21, 1995 |
| Grant date | May 12, 1998 |
| Priority date | — |
| Expiry date | Sep 21, 2015 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/36
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A bias generator is tested in an I.sub.DDQ -scheme by applying each respective one of the bias voltages to a respective PFET that is individually gated by a respective NFET. This permits measuring the quiescent currents. Any deviation in the bias voltages is translated into a deviation of the quiescent current.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.