Semiconductor device balancing thermal expansion coefficient mismatch
US5751552A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 6, 1997 |
| Grant date | May 12, 1998 |
| Priority date | — |
| Expiry date | May 6, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2224/48091
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A hybrid multi-chip module includes semiconductor chips (27, 31) bonded to a base plate (24). The base plate includes a substrate (11) having two surfaces (12, 13) and a conductive material (16) molded on the two surfaces (12, 13). A coefficient of thermal expansion (CTE) mismatch between the substrate (11) and the conductive material (16) at the first surface (12) is balanced by a similar, but opposite, CTE mismatch between the substrate (11) and the conductive material (16) at the second surface (13). The CTE mismatch balance across the base plate (24) produces a base plate (24) having a substantially planar form at high temperatures.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.