Ferroelectric memory devices and method for testing them
US5751628A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 20, 1996 |
| Grant date | May 12, 1998 |
| Priority date | — |
| Expiry date | Aug 20, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/22
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory cell comprises a ferroelectric capacitor, first main memory cells are connected to a first bit line, a first reference memory cell is connected to a second bit line, second main memory cells are connected to the second bit line, and a second reference memory cell is connected to the first bit line. When a first operation mode is selected by a control circuit comprising NAND gates and NOR gates, first main memory cells and first reference memory cell are selected, and when a second operation mode is selected, first main memory cells and second main memory cells are selected. Thus, by switching the operation between the two operation modes, a ferroelectric memory device that has stable operation at a low voltage and high integration at a high voltage is provided.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.