High speed memory output circuitry and methods for implementing same
US5751649A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 26, 1997 |
| Grant date | May 12, 1998 |
| Priority date | — |
| Expiry date | Feb 26, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/1051
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Disclosed is a latch sense amplifier output buffer for amplifying a data signal read from a memory. The latch sense amplifier output buffer includes a sense amplifier core having an amplifier circuit. The amplifier circuit provides amplification on the data signal read from a random access memory cell location. The sense amplifier core is preferably configured to generate an amplified data signal. Further included is an output data latching circuit that is configured to substantially simultaneously store the amplified data signal and generate an output data signal. An output buffer core includes an output driver circuit having a pull up transistor and a pull down transistor. The output driver circuit substantially concurrently receives the amplified data signal from the sense amplifier core and the output data signal from the output data latching circuit. The amplified data signal provides a fast turnoff to the pull up or pull down transistor, to thereby generate a rapid output at an output node coupled to the other pull up or pull down transistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.