Artisan Components, Inc.
🏢 View company profile →50Patents
0Active
50Granted
35Portfolio score
Filing activity: Feb 11, 1997 → Sep 24, 2003
Most-cited patents
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US6477695B1 | Methods for designing standard cell transistor structures | Physics | 202 | Expired |
| US6957402B2 | Yield maximization in the manufacture of integrated circuits | Physics | 195 | Expired |
| US6445049B1 | Cell based array comprising logic, transfer and drive cells | Emerging Cross-Sectional Technologies | 119 | Expired |
| US6044481A | Programmable universal test interface for testing memories with different test methodologies | Physics | 46 | Expired |
| US5999482A | High speed memory self-timing circuitry and methods for implementing the same | Physics | 35 | Expired |
| US5968192A | Programmable universal test interface and method for making the same | Physics | 29 | Expired |
| US6550047B1 | Semiconductor chip input/output cell design and automated generation methods | Physics | 22 | Expired |
| US6731135B2 | Low voltage differential signaling circuit with mid-point bias | Electricity | 20 | Expired |
| US6966012B1 | Memory column redundancy circuitry and method for implementing the same | Physics | 18 | Expired |
| US5965925A | Integrated circuit layout methods and layout structures | Electricity | 18 | Expired |
| US6448631B2 | Cell architecture with local interconnect and method for making same | Electricity | 17 | Expired |
| US6667917B1 | System and method for identification of faulty or weak memory cells under simulated extreme operating conditions | Physics | 17 | Expired |
| US6292927A | Reduction of process antenna effects in integrated circuits | Electricity | 17 | Expired |
| US6446250B1 | Input/output cell generator | Physics | 16 | Expired |
| US6973605B1 | System and method for assured built in self repair of memories | Physics | 16 | Expired |
| US6696852B1 | Low-voltage differential I/O device | Electricity | 14 | Expired |
| US6865119B2 | Negatively charged wordline for reduced subthreshold current | Physics | 13 | Expired |
| US6222791A | Slew tolerant clock input buffer and a self-timed memory core thereof | Physics | 12 | Expired |
| US6594813B1 | Cell architecture with local interconnect and method for making same | Electricity | 12 | Expired |
| US6016390A | Method and apparatus for eliminating bitline voltage offsets in memory devices | Physics | 12 | Expired |
| US5751649A | High speed memory output circuitry and methods for implementing same | Physics | 12 | Expired |
| US6640330B1 | System and method for setup and hold characterization in integrated circuit cells | Physics | 10 | Expired |
| US6432726B1 | Method and apparatus for reducing process-induced charge buildup | Electricity | 8 | Expired |
| US6470304B1 | Method and apparatus for eliminating bitline voltage offsets in memory devices | Physics | 8 | Expired |
| US5881008A | Self adjusting pre-charge delay in memory circuits and methods for making the same | Physics | 8 | Expired |
Source: USPTO / EPO open patent data. Counts and citation impact are objective bibliographic measures.