Method of manufacturing semiconductor chip package
US5753532A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Aug 29, 1996 |
| Grant date | May 19, 1998 |
| Priority date | — |
| Expiry date | Aug 29, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/181
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for manufacturing semiconductor chip package comprising steps of: (a) preparing a lead frame which comprises a pair of opposing side rails which have a plurality of through holes on their upper surface; a die pad onto which a chip will be mounted; a pair of rows of leads, each row being disposed at both sides of the die pad at a distance; and tiebars for mechanically and integrally connecting said die pad to said side rails; (b) filling a resin compound between leads and curing the resin compound to make dambars; (c) attaching said chip to an upper surface of said die pad, and electrically connecting said chip to leads; (d) encapsulating said chip, said die pad, said dambars, a part of said leads and a part of said tiebars to give a package body which is still attached to said lead frame; and (e) cutting said tiebars from lead frame to separate an individual package; and (f) forming leads extending from the package to have an appropriate bend shape is provided.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.