Sung-Min Sim
14Patents
7h-index
24Co-inventors
62Inventor score
Filing activity: Jul 26, 1994 → Jan 17, 2008
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US7151009B2 | Method for manufacturing wafer level chip stack package | Electricity | 328 | Expired |
| US5753532A | Method of manufacturing semiconductor chip package | Electricity | 185 | Expired |
| US5840614A | Method of producing a semiconductor wafer using ultraviolet sensitive tape | Electricity | 28 | Expired |
| US5543493A | Method for treating a polyimide surface | Chemistry; Metallurgy | 11 | Expired |
| US7205660B2 | Wafer level chip scale package having a gap and method for manufacturing the same | Electricity | 10 | Expired |
| US7307342B2 | Interconnection structure of integrated circuit chip | Electricity | 8 | Expired |
| US5933708A | Lead-on-chip semiconductor package and method for making the same | Electricity | 7 | Expired |
| US5633206A | Process for manufacturing lead frame for semiconductor package | Emerging Cross-Sectional Technologies | 7 | Expired |
| US7312143B2 | Wafer level chip scale package having a gap and method for manufacturing the same | Electricity | 5 | Active |
| US6423654B1 | Method of manufacturing a semiconductor device having silicon oxynitride passavation layer | Emerging Cross-Sectional Technologies | 5 | Expired |
| US7855144B2 | Method of forming metal lines and bumps for semiconductor devices | Electricity | 4 | Active |
| US7524763B2 | Fabrication method of wafer level chip scale packages | Electricity | 3 | Expired |
| US7732319B2 | Interconnection structure of integrated circuit chip | Electricity | 2 | Active |
| US7825495B2 | Semiconductor chip structure, method of manufacturing the semiconductor chip structure, semiconductor chip package, and method of manufacturing the semiconductor chip package | Electricity | 2 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.