Memory cell array with a self-aligned, buried bit line

US5753551A · kind A · utility

Assignee

• VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION · TW

Inventor

• Janmye Sung · Taipei, TW

Key dates

• Filing date: Nov 25, 1996
• Grant date: May 19, 1998
• Expiry date: Nov 25, 2016

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10B12/31

Abstract

A method for forming memory cells, featuring a bit line, embedded in an insulator filled, shallow trench, has been developed. Self-alignment of the buried bit line, to a source and drain region of a transfer gate transistor, is obtained via outdiffusion of a doped polysilicon layer, used as part of the buried bit line, composite layer.