Method of fabricating a MIS transistor
US5753556A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 29, 1996 |
| Grant date | May 19, 1998 |
| Priority date | — |
| Expiry date | Mar 29, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/859
Abstract
A CMIS transistor suitable for device miniaturization, elimination of degradation of operational characteristics by hot carrier effect, and elimination of decrease of threshold voltage caused by short channel effect, includes a laterally spreading N-type diffusion region having an impurity concentration level higher than P-type and N-type wells but lower than source and drain regions, such that the N-type diffusion region extends laterally into a part located immediately below an edge of an insulating gate and has a depth smaller than a depth of the source and drain regions. The device is thereby capable of increasing the width of depletion layer at the bottom of the source and drain regions while maintaining effectiveness as a punch-thorough stopper. Thereby, the junction capacitance at the source and drain regions is reduced and the operational speed of the device improved in the P-channel transistor part in the device. In the N-channel transistor part, an effective suppression of punch-through is achieved because of the small diffusion depth of the N-type diffusion region. Thereby, the decrease of threshold voltage caused by the short channel effect is effectively eliminated eve…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.