Advanced damascene planar stack capacitor fabrication method
US5753948A · kind A · utility
44Cited by
11References
8Claims
0Family size
Assignee
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Key dates
| Filing date | Nov 19, 1996 |
| Grant date | May 19, 1998 |
| Priority date | — |
| Expiry date | Nov 19, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D1/714
Abstract
Capacitor storage charge can be increased by increasing storage node area. A high aspect surface ratio stack capacitor is produced without increasing overall cell dimensions. The node is formed with layers of low doped and high doped concentration borophosphosilicate glass which is deposited by a single process step with precise nanometer dimensions, are selectively etched so that either doped or undoped layers will have a higher etch rate. This etching creates finger-like projections in the node, which provide for greater surface area using a very simplified process requiring fewer processing steps.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.