Method and apparatus for correcting a multilevel cell memory by using interleaving
US5754566A · kind A · utility
44Cited by
4References
23Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 6, 1996 |
| Grant date | May 19, 1998 |
| Priority date | — |
| Expiry date | Sep 6, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for correcting errors in a multilevel cell memory is described. A multilevel cell memory is comprised of multilevel cells, each capable of storing two or more bits of data. A plurality of data bits is received by the multilevel cell memory. The plurality of data bits are sorted into two or more data words. Error correction codes are generated for each of the two or more data words. A memory element bit pattern is formed that comprises one bit from each of the two or more data words. A charge state associated with the memory element bit pattern is stored in one of the multilevel cells.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.