Write reduction in flash memory systems through ECC usage
US5754567A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Oct 15, 1996 |
| Grant date | May 19, 1998 |
| Priority date | — |
| Expiry date | Oct 15, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/7207
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A nonvolatile memory system emulates a magnetic hard disk drive and includes an array of nonvolatile memory cells, such as flash memory cells, organized into sets, such as sectors. A buffer, such as a random access memory, stores a first set of data to be written to the array. Error correction code (ECC) circuitry receives the first set of data and calculates first ECC check bits representative of the first set of data. ECC comparison circuitry compares the first ECC check bits with second ECC check bits representative of a second set of data stored in the array to generate an ECC comparison signal having a first state indicative of a match between the first and second ECC check bits and a second state indicative of a miscomparison between the first and second ECC check bits.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.