Low-latency memory indexing method and structure
US5754819A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 28, 1994 |
| Grant date | May 19, 1998 |
| Priority date | — |
| Expiry date | Jul 28, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0864
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A significant reduction in the latency between the time the addressed components of memory are ready and the time addressed data is available to the address components of memory is achieved by processing the raw address information faster than the addition used in the prior art. XOR memory addressing replaces the addition of the base and offset address components with an XOR operation, eliminating carry propagation and reducing overall latency. In another embodiment, a sum-addressed memory (SAM) also eliminates the carry propagation and thus reduce the latency while providing the correct base+offset index to access the memory word line corresponding to the correct addition; thus a SAM causes no XOR duplicate problems.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.