System and method of establishing error precedence in a computer system
US5758065A · kind A · utility
18Cited by
16References
3Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 30, 1995 |
| Grant date | May 26, 1998 |
| Priority date | — |
| Expiry date | Nov 30, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/079
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system and method of establishing error precedence in a computer system which determine a first error to occur. The system determines the order of occurrence of errors in a computer system and includes error precedence modules which record and order errors that occur on a first bus with error that occur on a second bus. Diagnostic processing circuitry reads the errors stored within the error precedence modules and their order of occurrence and determines which bus the first error occurred on.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.