Method and system for increased system memory concurrency in a multi-processor computer system utilizing concurrent access of reference and change bits
US5758120A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 20, 1996 |
| Grant date | May 26, 1998 |
| Priority date | — |
| Expiry date | Aug 20, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/1027
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and system for increasing memory concurrency in a multiprocessor computer system which includes system memory, multiple processors coupled together via a bus, each of the processors including multiple processor units for executing multiple instructions and for performing read, write and store operations and an associated Translation Lookaside Buffer (TLB) for translating effective addresses into real memory addresses within the system memory. Multiple page table entries are provided within a page table within the system memory which each include multiple individually accessible fields, an effective address and an associated real memory address for a selected system memory location. A reference bit is provided within a first individually accessible field in each page table entry and this reference bit is utilized to indicate if an associated system memory location has been accessed for a read or write operation. A change bit is provided within a second individually accessible field within each page table entry and this change bit is utilized to indicate if an associated system memory location has been modified by a write operation. By storing the reference bit and change bi…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.