Register to memory data transfers with field extraction and zero/sign extension based upon size and mode data corresponding to employed address register
US5758195A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jun 7, 1995 |
| Grant date | May 26, 1998 |
| Priority date | — |
| Expiry date | Jun 7, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3885
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A data processing system including a data-memory storing data words having a first data size, and a data processor having an address generator generating addresses pointing to data of a second data size smaller than the first data size. The data processing system enables a data transfer by supplying an address to the data memory with zeros substituted for a predetermined number of least significant bits. The data processor receives a data word of the first data size corresponding to the altered address. The data processor stores data of a selected processor data size into a selected data register. If the processor data size is smaller than the first data size, then the date register stores a selected a subset of bits of the data word dependent upon the processor data size and the predetermined number of least significant address bits of said address. The selected processor data size is stored in a qualifier register which may be one of a plurality of qualifier registers corresponding to an address register used to generate the address. The data memory includes a plurality of write strobe inputs. The data processor repeats data recalled from a selected data registers of the selected…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.