Method of fabricating self-aligned contacts and local interconnects in CMOS and BICMOS processes using chemical mechanical polishing (CMP)

US5759882A · kind A · utility

Assignee

• NATIONAL SEMICONDUCTOR CORPORATION · US

Inventors

• Dah-Bin Kao · Palo Alto, US
• John M. Pierce · Clarkston, US

Key dates

• Filing date: Oct 16, 1996
• Grant date: Jun 2, 1998
• Expiry date: Oct 16, 2016

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L21/768
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A method of fabricating external contacts in an integrated circuit structure utilizes chemical mechanical polishing (CMP). The structure includes an active device substrate region defined by field oxides. First and second diffusions formed in the active region define a substrate surface region therebetween. In accordance with the method, a layer of amorphous or polycrystalline silicon is formed in contact with the diffusion regions, subjected to a chemical mechanical polishing (CMP) step and then etched to form external contacts. The process flow can be applied to CMOS technologies and adapted to bipolar technologies to provide a BiCMOS flow.