GaAs power semiconductor device operating at a low voltage and method for fabricating the same
US5760418A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 19, 1997 |
| Grant date | Jun 2, 1998 |
| Priority date | — |
| Expiry date | Mar 19, 2017 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S977/89
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Disclosed is a GaAs power semiconductor device operating at a low voltage and a method for fabricating the device, the method comprising the steps of sequentially forming a first undoped GaAs buffer layer, a superlattice layer, a second undoped GaAs buffer layer, a channel layer and a surface passivation layer on a semi-insulating GaAs substrate; etching a plurality of layers formed on the substrate using a device isolating mask so as to electrically isolate elements; selectively etching the surface passivation layer to form contact holes for source/drain formation and forming ohmic metallic layers in the contact holes; sequentially removing the surface passivation layer and the channel layer to some deep extent to form a contact hole for gate formation between the source and the drain; forming a gate in the contact hole and at the same time forming source and drain electrodes on the ohmic metallic layers; depositing a first SiN layer over the gate, the source and drain electrodes and the surface passivation layer; selectively etching the first SiN layer so as to expose top surfaces only of the source and drain electrodes; plating a gold layer only on the source and drain electrode…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.