Alignment mark pattern for semiconductor process
US5760484A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 11, 1997 |
| Grant date | Jun 2, 1998 |
| Priority date | — |
| Expiry date | Feb 11, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An alignment mark for increasing the accuracy of an alignment includes a cross pattern, two horizontal line patterns having serrated shape. The cross pattern is typically formed over a scribe line for alignment in semiconductor process. The cross pattern includes a vertical line and a horizontal line. The vertical line is vertical to the scribe line while the horizontal line is parallel to the scribe line. The horizontal patterns which are parallel to the scribe line are respectively connected to one end of the vertical line. The horizontal patterns have serrated patterns which are used to change the shape of a noise signal. The high of the serrated shape pattern is about 3 micro meters while the width of the serrated shape pattern is about 3 micro meters.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.