MOSEL VITELIC INC.
473Patents
11Active
473Granted
42Portfolio score
Filing activity: Jul 16, 1992 → Jun 30, 2020 · 3 expiring within 5 years
Most-cited patents
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US6306772A | Deep trench bottle-shaped etching using Cl2 gas | Electricity | 172 | Expired |
| US6265269A | Method for fabricating a concave bottom oxide in a trench | Electricity | 100 | Expired |
| US6355524B1 | Nonvolatile memory structures and fabrication methods | Electricity | 98 | Expired |
| US5701013A | Wafer metrology pattern integrating both overlay and critical dimension features for SEM or AFM measurements | Electricity | 97 | Expired |
| US6133597A | Biasing an integrated circuit well with a transistor electrode | Electricity | 90 | Expired |
| US6303436A | Method for fabricating a type of trench mask ROM cell | Emerging Cross-Sectional Technologies | 81 | Expired |
| US5452261A | Serial address generator for burst memory | Physics | 69 | Expired |
| US6008106A | Micro-trench oxidation by using rough oxide mask for field isolation | Electricity | 59 | Expired |
| US6040216A | Method (and device) for producing tunnel silicon oxynitride layer | Electricity | 55 | Expired |
| US5811358A | Low temperature dry process for stripping photoresist after high dose ion implantation | Electricity | 53 | Expired |
| US6194272A | Split gate flash cell with extremely small cell size | Emerging Cross-Sectional Technologies | 50 | Expired |
| US5827747A | Method for forming LDD CMOS using double spacers and large-tilt-angle ion implantation | Emerging Cross-Sectional Technologies | 49 | Expired |
| US6008515A | Stacked capacitor having improved charge storage capacity | Electricity | 47 | Expired |
| US5672243A | Antireflection coating for highly reflective photolithographic layers comprising chromium oxide or chromium suboxide | Emerging Cross-Sectional Technologies | 45 | Expired |
| US6440792B1 | DRAM technology of storage node formation and no conduction/isolation process of bottle-shaped deep trench | Electricity | 45 | Expired |
| US5760484A | Alignment mark pattern for semiconductor process | Electricity | 41 | Expired |
| US6415374B1 | System and method for supporting sequential burst counts in double data rate (DDR) synchronous dynamic random access memories (SDRAM) | Physics | 40 | Expired |
| US5843822A | Double-side corrugated cylindrical capacitor structure of high density DRAMs | Electricity | 40 | Expired |
| US5516711A | Method for forming LDD CMOS with oblique implantation | Electricity | 39 | Expired |
| US6184093A | Method of implementing differential gate oxide thickness for flash EEPROM | Emerging Cross-Sectional Technologies | 38 | Expired |
| US6191997A | Memory burst operations in which address count bits are used as column address bits for one, but not both, of the odd and even columns selected in parallel. | Physics | 35 | Expired |
| US6232171A | Technique of bottle-shaped deep trench formation | Electricity | 35 | Expired |
| US6123865A | Method for improving etch uniformity during a wet etching process | Electricity | 33 | Expired |
| US5972754A | Method for fabricating MOSFET having increased effective gate length | Electricity | 33 | Expired |
| US6743675B2 | Floating gate memory fabrication methods comprising a field dielectric etch with a horizontal etch component | Electricity | 32 | Expired |
Source: USPTO / EPO open patent data. Counts and citation impact are objective bibliographic measures.