Contamination monitoring using capacitance measurements on MOS structures
US5760594A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Sep 30, 1996 |
| Grant date | Jun 2, 1998 |
| Priority date | — |
| Expiry date | Sep 30, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L22/12
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A method for monitoring contamination in a semiconductor wafer uses a capacitance-frequency measurement on MOS structures to calculate an impurity concentration. The silicon substrate along with an oxide layer is first biased into the inversion region using a variable frequency waveform generator superimposed upon a DC voltage bias. Next, the capacitance of the wafer is measured as a function of the varying frequency in order to develop a capacitance versus frequency curve. From this frequency response, a bandwidth (BW) is measured at a particular normalized capacitance point. The impurity concentration N is then derived using the formula N=G.times.BW, where G is the correlation constant. With an a priori knowledge of impurity concentration, N, the constant G may be derived by measuring a bandwidth of the capacitance versus frequency curve. Once the constant G is determined, future evaluation of impurity concentration can be made by a capacitance measurement. The method can be used on finished product wafers or as a routine monitoring tool on pre-processed wafers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.