PMOS single-poly non-volatile memory structure

US5761121A · kind A · utility

Assignee

• Programmable Microelectronics Corporation · US

Inventor

• Shang-De Ted Chang · Fremont, US

Key dates

• Filing date: Oct 31, 1996
• Grant date: Jun 2, 1998
• Expiry date: Oct 31, 2016

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D30/685

Abstract

A P-channel single-poly non-volatile memory cell having P+ source and P+ drain regions and a channel extending therebetween is formed in an N-type well. An overlying poly-silicon floating gate is separated from the N-well by a thin oxide layer. A P-type diffusion region is formed in a portion of the N-well underlying the floating gate and is thereby capacitively coupled to the floating gate. Within this P-type diffusion area lies an N-type diffusion area which serves as the control gate for the cell. The P-type diffusion region electrically isolates the control gate from the N-well such that voltages may be applied to the control gate in excess of those applied to the N-well without creating a current path from the control gate to the N-well. Programming is accomplished by coupling a sufficient voltage to the floating gate via the control gate while biasing the source and drain regions so as to cause the tunneling of electrons from the P+ drain region of the cell to the floating gate. In some embodiments, an additional P-type diffusion region underlying the floating gate and separated therefrom by a layer of tunnel oxide serve as an erase gate for the memory cell. In such embodimen…