Dynamic RAM
US5761149A · kind A · utility
Assignees
Inventors
Key dates
| Filing date | Jul 12, 1996 |
| Grant date | Jun 2, 1998 |
| Priority date | — |
| Expiry date | Jul 12, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/488
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A dynamic RAM is provided with a main word lines; a plurality of subsidiary word lines which are arranged in the direction of bit lines crossing the main word line and to which a plurality of dynamic memory cells are connected; a plurality of subsidiary word selection lines which are extended so as to perpendicularly intersect the main word line and through which a selection signal for selecting one of the plurality of subsidiary word lines is transmitted; and a logic circuit for receiving a selection signal from the main word line and a selection signal from each of the subsidiary word selection lines to thereby form a selection signal for selecting one of the subsidiary word lines. In the dynamic RAM, the voltage level of each of the main word line and the subsidiary word selection lines is made to be equal to the ground potential when the line is in a not-selected state.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.