Scan based path delay testing of integrated circuits containing embedded memory elements

US5761215A · kind A · utility

Assignee

• Motorola, Inc. · US

Inventors

• Daniel M. McCarthy · Phoenix, US
• Paul William Hollis · Austin, US
• Ruey J. Yu · Ambler, US
• Renny L. Eisele · West Lake Hills, US

Key dates

• Filing date: Jul 7, 1997
• Grant date: Jun 2, 1998
• Expiry date: Jul 7, 2017

Classification

• Technology area (CPC G): Physics
• CPC primary: G01R31/31858
• WIPO field: Measurement
• WIPO sector: Instruments

Abstract

Accurate delay testing of integrated circuits containing memory arrays embedded in combinational logic utilizes actual memory array timing. Actual memory timing signals provide the timing for bypassing the memory in SCAN Mode. The result is that simulated memory accesses during SCAN Mode testing have the same timing as actual memory accesses have during functional mode operation. Thus delay testing during SCAN Mode through paths containing both combinational logic and memory arrays accurately determines path delays.