Bit error measurement system
US5761216A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 10, 1997 |
| Grant date | Jun 2, 1998 |
| Priority date | — |
| Expiry date | Feb 10, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/24
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A bit error measurement system provides means for generating test patterns, multiplexing means and means for specifying and recording a pattern position. In a first aspect, a bit error measurement system has a pattern generator having M channels of pattern generation and a pattern generation controller 10 for controlling the pattern generation in the M channels so that when one channel is selected to generate a pattern the other channels are controlled to be waiting. In a second aspect, a clock frequency difference detector 150 is provided for counting a frequency of an input clock 111 and comparing the results with the frequency at the time of previous switching to detect whether the frequency change is greater than a predetermined value to judge whether the system is in a measurement state and to permit or prohibit a switching operation of a clock switch circuit. In a third aspect, a pattern position recording part 210 is provided to store pattern position information of a reference pattern generator 262 when an error detection signal 265.sub.a is received from a comparator 265.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.