Digital architecture for recovering NRZ/NRZI data
US5761254A · kind A · utility
46Cited by
7References
15Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jan 31, 1996 |
| Grant date | Jun 2, 1998 |
| Priority date | — |
| Expiry date | Jan 31, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/0337
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for generating a data signal from a transmitted data signal that has been distorted by duty cycle jitter. A locally generated symbol signal is propagated in a delay line such that taps along the delay line emit bit phase signals that are used to clock transitions of the data signal. The position of the data transitions are accorded a numerical value with reference to the bit boundaries and numerically averaged to determine a most desired time to detect the logic level of the data sample.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.