Computer system employing a bus conversion bridge for interfacing a master device residing on a multiplexed peripheral bus to a slave device residing on a split-address, split-data multiplexed peripheral bus
US5761443A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jun 7, 1995 |
| Grant date | Jun 2, 1998 |
| Priority date | — |
| Expiry date | Jun 7, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4018
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A multiple-transaction peripheral bus is provided with multiplexed address and data lines which is particularly adapted for portable applications. The multiple-transaction peripheral bus accommodates compatibility with existing hardware designs for a higher performance bus system with minimal conversion logic. A bus conversion bridge provides an interface between a 32-bit Peripheral Component Interconnect (PCI) bus and a 16-bit transaction Address/Data (A/D) which is associated with half the number of multiplexed address/data lines in comparison with the 32-bit PCI bus. The PCI bus accommodates data transfers between master and slave devices associated therewith, as does the narrower multiple-transaction A/D bus. The bus conversion bridge accommodates data transfers between the two buses, allowing a master device on one bus to communicate with a slave device on the other bus. The bus conversion bridge accomplishes this by 1) splitting both the 32-bit address/4-bit bus command and 32-bit data/4-bit byte enables received from the PCI bus during respective address and data phases into separate 16-bit/2-bit packets, and transmitting these packets over the multiple-transaction A/D bus d…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.