Uwe Kranich
18Patents
12h-index
2Co-inventors
68Inventor score
Filing activity: Dec 18, 1992 → Jan 24, 2022
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US6185675A | Basic block oriented trace cache utilizing a basic block sequence buffer to indicate program order of cached basic blocks | Physics | 86 | Expired |
| US6651163B1 | Exception handling with reduced overhead in a multithreaded multiprocessing system | Physics | 82 | Expired |
| US6574725B1 | Method and mechanism for speculatively executing threads of instructions | Physics | 80 | Expired |
| US7012604B1 | System architecture for high speed ray tracing | Physics | 76 | Expired |
| US6157996A | Processor programably configurable to execute enhanced variable byte length instructions including predicated execution, three operand addressing, and increased register space | Physics | 50 | Expired |
| US6456891B1 | System and method for transparent handling of extended register states | Physics | 49 | Expired |
| US5900022A | Apparatus and method for reducing the cache miss penalty in a virtual addressed memory system by using a speculative address generator and an accurate address generator | Physics | 37 | Expired |
| US5524225A | Cache system and method for providing software controlled writeback | Physics | 35 | Expired |
| US6230259A | Transparent extended state save | Physics | 33 | Expired |
| US5850534A | Method and apparatus for reducing cache snooping overhead in a multilevel cache system | Physics | 30 | Expired |
| US5761443A | Computer system employing a bus conversion bridge for interfacing a master device residing on a multiplexed peripheral bus to a slave device residing on a split-address, split-data multiplexed peripheral bus | Physics | 16 | Expired |
| US5761709A | Write cache for servicing write requests within a predetermined address range | Physics | 15 | Expired |
| US5752263A | Apparatus and method for reducing read miss latency by predicting sequential instruction read-aheads | Physics | 6 | Expired |
| US7890740B2 | Processor comprising a first and a second mode of operation and method of operating the same | Physics | 1 | Active |
| US11252333B2 | Production shot design system | Physics | 1 | Active |
| US7689809B2 | Transparent return to parallel mode by rampoline instruction subsequent to interrupt processing to accommodate slave processor not supported by operating system | Physics | 1 | Active |
| US5546560A | Device and method for reducing bus activity in a computer system having multiple bus-masters | Physics | 1 | Expired |
| US11785332B2 | Production shot design system | Physics | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.