Bus arbiter method and system
US5761452A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 18, 1996 |
| Grant date | Jun 2, 1998 |
| Priority date | — |
| Expiry date | Mar 18, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/364
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An improved bus arbitration system comprising an information bus, first and second bus masters connected to the bus and a bus arbiter for controlling ownership of the bus. The first bus master is adapted to perform speculative pre-fetching and has a first REQ signal for requesting ownership of the bus and an SP signal for indicating when a bus ownership request is for a speculative pre-fetch. The second bus master has a second REQ signal for requesting ownership of the bus. The bus arbiter is configured such that when the first bus master asserts its REQ signal and its SP signal and the second bus master asserts its REQ signal, the bus arbiter assigns higher priority to the second bus master in response to the SP signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.