Apparatus and method to speculatively initiate primary memory accesses
US5761708A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 31, 1996 |
| Grant date | Jun 2, 1998 |
| Priority date | — |
| Expiry date | May 31, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0884
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A central processing unit with an external cache controller and a primary memory controller is used to speculatively initiate primary memory access in order to improve average primary memory access times. The external cache controller processes an address request during an external cache latency period and selectively generates an external cache miss signal or an external cache hit signal. If no other primary memory access demands exist at the beginning of the external cache latency period, the primary memory controller is used to speculatively initiate a primary memory access corresponding to the address request. The speculative primary memory access is completed in response to an external cache miss signal. The speculative primary memory access is aborted if an external cache hit signal is generated or a non-speculative primary memory access demand is generated during the external cache latency period.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.