Kevin Normoyle
51Patents
23h-index
53Co-inventors
91Inventor score
Filing activity: Nov 14, 1985 → Aug 24, 2023
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US5655100A | Transaction activation processor for controlling memory transaction execution in a packet switched cache coherent multiprocessor system | Physics | 275 | Expired |
| US5634068A | Packet switched cache coherent multiprocessor system | Physics | 119 | Expired |
| US4939638A | Time sliced vector processing | Physics | 113 | Expired |
| US5905998A | Transaction activation processor for controlling memory transaction processing in a packet switched cache coherent multiprocessor system | Physics | 110 | Expired |
| US5644753A | Fast, dual ported cache controller for data processors in a packet switched cache coherent multiprocessor system | Physics | 103 | Expired |
| US5684977A | Writeback cancellation processing system for use in a packet switched cache coherent multiprocessor system | Physics | 88 | Expired |
| US5692197A | Method and apparatus for reducing power consumption in a computer network without sacrificing performance | Physics | 82 | Expired |
| US5657472A | Memory transaction execution system and method for multiprocessor system having independent parallel transaction queues associated with each processor | Physics | 74 | Expired |
| US7337339B1 | Multi-level power monitoring, filtering and throttling at local blocks and globally | Emerging Cross-Sectional Technologies | 67 | Active |
| US5884100A | Low-latency, high-throughput, integrated cache coherent I/O system for a single-chip processor | Physics | 66 | Expired |
| US7203890B1 | Address error detection by merging a polynomial-based CRC code of address bits with two nibbles of data or data ECC bits | Physics | 64 | Expired |
| US5852608A | Structure and method for bi-directional data transfer between asynchronous clock domains | Physics | 63 | Expired |
| US5893153A | Method and apparatus for preventing a race condition and maintaining cache coherency in a processor with integrated cache memory and input/output control | Physics | 51 | Expired |
| US5892957A | Method and apparatus for interrupt communication in packet-switched microprocessor-based computer system | Physics | 47 | Expired |
| US7437597B1 | Write-back cache with different ECC codings for clean and dirty lines with refetching of uncorrectable clean lines | Physics | 45 | Active |
| US5689713A | Method and apparatus for interrupt communication in a packet-switched computer system | Physics | 40 | Expired |
| US5706463A | Cache coherent computer system that minimizes invalidation and copyback operations | Physics | 35 | Expired |
| US7376800B1 | Speculative multiaddress atomicity | Physics | 34 | Expired |
| US5070475A | Floating point unit interface | Physics | 28 | Expired |
| US7332929B1 | Wide-scan on-chip logic analyzer with global trigger and interleaved SRAM capture buffers | Physics | 27 | Active |
| US5761708A | Apparatus and method to speculatively initiate primary memory accesses | Physics | 26 | Expired |
| US5710891A | Pipelined distributed bus arbitration system | Physics | 25 | Expired |
| US7398449B1 | Encoding 64-bit data nibble error correct and cyclic-redundancy code (CRC) address error detect for use on a 76-bit memory module | Physics | 25 | Active |
| US5987081A | Method and apparatus for a testable high frequency synchronizer | Electricity | 23 | Expired |
| US4949247A | System for transferring multiple vector data elements to and from vector memory in a single operation | Physics | 18 | Expired |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.