Cache-based computer system employing a peripheral bus interface unit with cache write-back suppression and processor-peripheral communication suppression for data coherency
US5761725A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 10, 1996 |
| Grant date | Jun 2, 1998 |
| Priority date | — |
| Expiry date | Sep 10, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0835
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A peripheral bus interface unit is provided that includes a data storage unit for temporarily storing data written from a peripheral unit, and a control unit that executes a write cycle on a system bus to transfer the data into a system memory. The control unit blocks certain communications, such as polling and interrupt communications between a microprocessor and the peripheral device if data temporarily stored within the data storage unit has not yet been transferred to the system memory. In addition, depending upon whether a complete line of data is to be transferred during the write cycle, the control unit either asserts or deasserts a snoop write-back signal. If the snoop write-back signal is asserted, a snoop write-back operation by, for example, a cache controller is allowed. If the snoop write-back signal is deasserted, a snoop write-back operation of the cache controller is suppressed. In one embodiment, a line monitor unit within the peripheral bus interface unit is employed to determine whether a full line of valid words are being transferred during a given cycle. An interrupt latch is also employed to detect an assertion of an interrupt signal generated by the periphera…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.