Control apparatus for a memory architecture using dedicated and shared memory segments
US5761727A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 2, 1996 |
| Grant date | Jun 2, 1998 |
| Priority date | — |
| Expiry date | Apr 2, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G2360/125
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
Disclosed is a memory control device with partitioned memory control for use on a computer system configured based on a shared main memory architecture. The memory control device comprises a main memory controller connected with two sets of access control buses used respectively for partitioned control of the main memory. The main memory is partitioned into a main system dedicated memory segment and a shared resource memory segment respectively for use by the CPU and the peripheral system. A shared data path circuit is used to control data flow on the buses. When the CPU and the peripheral system both want to gain access to the main memory at the same time, the two sets of buses work independently to respectively connect the CPU to the main system dedicated memory segment and the peripheral system to the shared resource memory segment in the main memory for simultaneous, partitioned access to the main memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.