Method of fabricating capacitor over bit line COB structure for a very high density DRAM applications

US5763306A · kind A · utility

Assignee

• VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION · TW

Inventor

• Hong-Hsiang Tsai · Hsinchu, TW

Key dates

• Filing date: Oct 24, 1997
• Grant date: Jun 9, 1998
• Expiry date: Oct 24, 2017

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10B12/033

Abstract

A method of creating a deep pocket, capacitor over bit line structure, used for high density, DRAM designs, has been developed. The process consists of creating silicon nitride covered, polysilicon bit line structures, on an insulator layer, contacting an underlying source and drain region. A series of layers are next deposited, and patterned, to form the initial phase of a storage node contact hole, terminating at the surface of the silicon nitride covered polysilicon bit line structures. After formation of insulator spacers, protecting the silicon nitride covered, polysilicon bit line structures, the final phase of the storage node contact hole is formed, between polysilicon bit line structures, using RIE procedures. A storage node structure, featuring an HSG silicon layer, is formed on the inside surface of the storage node contact hole, followed by the creation of a capacitor dielectric layer, and an upper electrode structure, resulting in a deep pocket, capacitor over bit line structure.