Process for fabricating semiconductor devices with shallowly doped regions using dopant compounds containing elements of high solid solubility
US5763319A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 5, 1996 |
| Grant date | Jun 9, 1998 |
| Priority date | — |
| Expiry date | Jun 5, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/601
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for manufacturing shallowly doped semiconductor devices. In the preferred embodiment, the method includes the steps of: (a) providing a substrate where the substrate material is represented by the symbol Es (element of the substrate); and (b) implanting the substrate with an ion compound represented by the symbol E1.sub.x Ed.sub.y, where E1 represents an element having high solubility in the substrate material with minimal detrimental chemical or electrical effects and can be the same element as the substrate element, Ed (dopant element) represents an element which is an electron acceptor or donor having high solubility limit in the substrate material, and x and y indicate the number of respective E1 and Ed atoms in the ion compound.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.